Flash memory is a type of non-volatile electronic data storage circuitry that can be electronically programmed to hold data and be erased repeatedly, thus well suitable as a rewritable data storage medium used in electronics and computer systems. NAND flash memory is a special type of flash memory that uses floating-gate transistors connected serially in a NAND gate fashion. The NAND flash memory technology is widely used in computer systems, digital cameras, portable music players, USB flash drives, memory cards, and SmartMedia™ cards.
NAND flash memories come in different capacities and electronic architectures depending on the manufacture, model, and technology used. For example, memory banks in a NAND flash memory device are arranged into blocks with sizes including but not limited to 16K, 128K, 256K, or 512K bytes. Each block is further organized into pages. The number of pages can be 32, 64, 128, or more with each page having a possible size of 256, 512, 1K, 2K, or 4K bytes. Other technical variations arise in other attributes such as block type, address cycles, and size of spare memory space.
In order to communicate with a NAND flash memory device, the aforementioned electronic characteristics of the NAND flash memory device must be known to the host system. These electronic characteristics become the interface parameters of a particular NAND flash memory device of a particular capacity, model and make coupled to the host system typically through a flash controller component. Thus, the flash controller component interfacing the NAND flash memory device must have knowledge of the NAND flash memory device's interface parameters including its address cycle, block type, page size, spare size, memory size, and block size.
Under the current state of technology, a typical electronic or computer system must store, in a separate memory, multiple sets of NAND flash memory interface parameter values of different manufactures and models that are supported. Upon the coupling of a NAND flash memory device, the matching set of interface parameter values is loaded into its flash controller. For this reason, system boot instruction codes necessary in initializing a computer processor cannot be stored in NAND flash based memory.
One solution to the above problem is to pre-configure the flash controller with a pre-defined set of NAND flash memory interface parameter values. However, the drawback is that only one manufacture and type of NAND flash memory will be accepted by the host system, or at least the pre-configured flash controller.
In the business of mass production of consumer electronics, it is particularly problematic for the manufacturing assembly lines to match the exact makes and models of NAND flash memories to voluminous product items, which can come in many different configurations with components sourced from many different suppliers. If the NAND flash interface parameters can be automatically detected, then multiple makes and/or models of NAND flash memories, regardless the differences in their interface parameters, can be paired with a flash controller without any pre-configuration.
The U.S. Patent Application Publication No. US 2008/0288715 discloses a method of hardware implementable NAND flash memory page size automatic detection and another method of software implementable detection. However, the disclosed hardware method, based on the difference in access protocol, can only estimate whether the page size is less than or equal 512 bytes or otherwise; and the disclosed software method relies on the use of automatic detection markers, which are small pieces data that are written to specific locations in the memory space of the NAND flash memory during manufacture at the manufacturer's discretion. Therefore, the NAND flash memory must be new in order for this software method to work.
The U.S. Pat. No. 7,657,696 also discloses a method for automatically detecting a plurality of parameters for a NAND flash memory. However, the U.S. Pat. No. 7,657,696 describes the detection of only some of the NAND flash memory parameters such as address cycle and page size without addressing other interface parameters necessary in facilitating a communication session with full range of functionality with a NAND flash memory device.
In the U.S. Patent Application Publication No. 2007/0067520, although a general flow of NAND flash parameters detection is described, it does not provide any specific methodology or mechanism for determining the interface parameter values of NAND flash memories of different manufacture and model.
Another problem associated with using flash memory to store system boot instruction codes is the operating speed mismatch between the computer processor and the flash memory. A typical computer processor can execute instructions far faster than a flash memory can retrieve and feed the processor the boot instruction codes stored in it, resulting in wasteful processor waiting cycles.
In order to narrow the operating speed difference between the computer processor and the flash memory, many system designs employ a cache hierarchy where a faster memory technology is used as intermediate data or instruction cache. One such design is include a bank of static random access memory (SRAM) in the flash controller. Because SRAM is costly and has much lower memory density, it is typical that only a relatively small amount is incorporated.
When the system boot instruction codes exceed the cache in size, the instruction codes can only be partially cached. It leads to the question of which part of the instruction codes should be cached at any point of time during the code execution. The U.S. Pat. No. 6,026,027 discloses an electronic memory system having a semi-permanent memory storage, a memory device for rapid data transfer and temporary memory storage, and controller for monitoring and controlling writes to the semi-permanent memory storage. In one of its examples, a flash memory and SRAM is used as the semi-permanent memory storage and the temporary memory storage respectively. This arrangement tends to increase the effective operational bandwidth of an implementation of flash memory; but the simplicity of its cache management process, in which data is read from cache only when the data is in the cache, the full potential benefit of a caching hierarchy is not realized.
A more advance cache management system is presented in the U.S. Pat. No. 7,493,447. The disclosed cache management system provides a sort of prediction for sequential program code such that the soon-to-be-executed instructions will be cached. However, the prediction is dependent on the type of instruction code branching or jumping, thus the cache management system is specific to the types of computer processor.